It is known that introduction of strain in semiconductor devices can enhance carrier mobility and therefore enhance drive current capability of such devices. For example, and not intended to be limiting, with silicon semiconductor based metal-oxide-semiconductor (MOS) field effect transistors (FETs) it is known that use of source-drain regions formed of a silicon-germanium (Si—Ge) alloy or mixture can provide compressive strain in the channel region located between the source and drain of PMOS devices. This strain can increase carrier mobility in the channel region and significantly improve overall device properties. However, many practical difficulties are encountered in implementing such structures. For example, and not intended to be limiting, bringing the strain inducing source-drain regions closer to the gate edges in order to enhance the localized strain beneath the gate often leads to integrity problems with the gate dielectric and reduced manufacturing yield. For these and other reasons there is an ongoing need for improved structures and methods for strain enhanced semiconductor devices, especially MOSFETs.